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Ordering number : EN4841C
CMOS LSI
LC74723, 74723M
On-Screen Display Controller
Overview
The LC74723 and LC74723M are on-screen display controller CMOS LSIs that display characters and patterns on a TV screen under microprocessor control. Characters are 8 x 8 dots, and a dot interpolation function is provided. The LC74723 can display 24 characters x 10 lines of text.
Package Dimensions
unit: mm 3067-DIP24S
[LC74723]
Features
* Screen structure: 24 characters x 10 lines (up to 240 characters) * Character structure: 8 (horizontal) x 8 (vertical) (interpolation function supported) * Character sizes: Two horizontal and two vertical sizes * Number of characters: 64 * Display start position: 64 horizontal and 64 vertical positions * Blinking: In character units * Blinking types: Two, with periods of 0.5 and 1.0 seconds * Blue background screen display: (in internal synchronization mode) * External control inputs: 8-bit serial input interface * Built-in sync separator circuit * Video output: Compound NTSC and PAL-M output * Packages: 24-pin plastic MFP (375 mil) 24-pin plastic DIP (300 mil)
SANYO: DIP24S
unit: mm 3045B-MFP24
[LC74723M]
SANYO: MFP24
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
63097HA (OT)/41596TH (OT)/83194TH (OT) No. 4841-1/12
LC74723, 74723M Pin Assignment
Pin Functions
Pin No. 1 2 3 4 5 6 7 Symbol VSS1 XtalIN XtalOUT CTRL1 CSYNOUT OSCIN OSCOUT Ground Crystal oscillator connection Crystal oscillator input switching Composite synchronization signal output LC oscillator Function Ground (digital system ground) Used either for connecting the external crystal and capacitor that are used for internal synchronization signal generation, or to input an external clock signal (2fsc or 4fsc). Switches the LC74723 between external clock input mode and crystal oscillator mode. Low = crystal oscillator mode, high = external clock mode Outputs a composite synchronization signal. Outputs the crystal oscillator clock on reset, i.e., when RST is low. Connections for the coil and capacitor that form the oscillator used to generate the character output dot clock. Outputs the result of judging whether or not there is an external synchronization signal. Outputs a high level when an external synchronization signal is present. Outputs the dot clock (LC oscillator) on reset, i.e., when RST is low. (The LC74723 can be set not to output this signal on reset using control data.) Enables serial data input. Serial data input is enabled when this input is low. There is a built-in pull-up resistor on this input (hysteresis input). Inputs the clock signal used for serial data input. There is a built-in pull-up resistor on this input (hysteresis input). Serial data input. There is a built-in pull-up resistor on this input (hysteresis input). Power supply (analog system power supply) for composite video signal level adjustment. Composite video signal output Must be either connected to ground or left open. Video signal input Power supply Sync separator circuit input Composite video signal input Power supply (+5 V: digital system power supply) Video signal input for the built-in sync separator circuit (When the built-in sync separator circuit is not used, input either the horizontal synchronization signal or the composite synchronization signal.) Description
8
SYNCJDG
External synchronization signal judgment output
9 10 11 12 13 14 15 16 17 18 19
CS SCLK SIN VDD2 CVOUT NC CVIN VDD1 SYNIN SEPC SEPOUT
Enable input Clock input Data input Power supply Video signal output
Sync separator circuit bias voltage Built-in sync separator circuit bias voltage monitor Composite synchronization signal output Outputs the built-in sync separator circuit's composite synchronization signal. (Outputs the SYNIN input signal when the built-in sync separator circuit is not used.) Inputs the vertical synchronization signal by integrating the output signal from the SEPOUT pin. An integration circuit must be connected between the SEPOUT pin and this pin. Hold at VDD1 if this input is unused.
20
SEPIN
Vertical synchronization signal input
Continued on next page. No. 4841-2/12
LC74723, 74723M
Continued from preceding page.
Pin No. 21 22 23 24 Symbol CTRL2 CTRL3 RST VDD1 Function NTSC/PAL-M switch input SEPIN input control Reset input Power supply (+5 V) Description Switches the synchronization signal generation between NTSC and PAL-M. Low = NTSC, high = PAL-M Controls whether the VSYNC signal is input to SEPIN. Low = Input VSYNC, high = do not input. System reset input There is a built-in pull-up resistor on this input (hysteresis input). Power supply (+5 V: digital system power supply)
Note: * Both the VDD1 pins (pins 16 and 24) must be connected.
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter Maximum supply voltage Maximum input voltage Maximum output voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD max VIN max VOUT max Pd max Topr Tstg VDD1, VDD2 All input pins CSYNOUT, SYNCJDG, SEPOUT Ta = 25C Conditions Ratings VSS - 0.3 to VSS + 7.0 VSS - 0.3 to VDD + 0.3 VSS - 0.3 to VDD + 0.3 350 -30 to +70 -40 to +125 Unit V V V mW C C
Allowable Operating Ranges at Ta = -30 to +70C
Parameter Supply voltage Symbol VDD1 VDD2 VIH1 VIH2 VIL1 VIL2 RPU VIN1 VIN2 VIN3 fosc1 fosc1 Oscillator frequency fosc1 fosc1 fosc2 VDD1 VDD2 RST, CS, SIN, SCLK CTRL1, CTRL2, CTRL3, SEPIN RST, CS, SIN, SCLK CTRL1, CTRL2, CTRL3, SEPIN Applies to the RST, CS, SIN, and SCLK pins and to the pins specified by options. CVIN; VDD1 = 5 V SYNIN; VDD1 = 5 V XtalIN (when external clock input is used) fin = 2fsc or 4fsc; VDD1 = 5 V XtalIN and XtalOUT oscillator pins (2fsc: NTSC) XtalIN and XtalOUT oscillator pins (4fsc: NTSC) XtalIN and XtalOUT oscillator pins (2fsc: PAL-M) XtalIN and XtalOUT oscillator pins (4fsc: PAL-M) OSCIN and OSCOUT oscillator pins (LC oscillator) 5 0.1 7.159 14.318 7.151 14.302 12 Conditions min 4.5 4.5 0.8 VDD1 0.7 VDD1 VSS - 0.3 VSS - 0.3 25 50 2.0 2.0 2.5 5.0 typ 5.0 5.0 max 5.5 1.27 VDD1 VDD1 + 0.3 VDD1 + 0.3 0.2 VDD1 0.3 VDD1 90 Unit V V V V V V k Vp-p Vp-p Vp-p MHz MHz MHz MHz MHz
Input high level voltage
Input low level voltage Pull-up resistance Composite video input voltage Input voltage
Note: When the XtalIN pin is used in clock input mode, be extremely careful of input noise.
Electrical Characteristics at Ta = -30 to +70C, VDD1 = 5 V unless otherwise specified
Parameter Input off leakage current Output off leakage current Output high level voltage Output low level voltage Symbol Ileak1 Ileak2 VOH1 VOL1 IIH IIL Current drain (operating) IDD1 IDD2 CVIN CVOUT CSYNOUT, SYNCJDG, SEPOUT; VDD1 = 4.5 V, IOH = -1.0 mA CSYNOUT, SYNCJDG, SEPOUT; VDD1 = 4.5 V, IOL = 1.0 mA RST, CS, SIN, SCLK, CTRL1, CTRL2, CTRL3, SEPIN; VIN = VDD1 CTRL1, CTRL2, CTRL3, OSCIN; VIN = VSS1 VDD1; All outputs open, Xtal: 7.159 MHz, LC: 8 MHz VDD2; VDD2 = 5 V -1 15 20 3.5 1.0 1 Conditions min typ max 1 1 Unit A A V V A A mA mA
Input current
Continued on next page. No. 4841-3/12
LC74723, 74723M
Continued from preceding page.
Parameter Sync level Symbol VSN VPD VCBL VCBH VRSL VRSH VBK0 VBK1 VCHA Conditions When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V min 0.69 0.89 1.28 1.47 0.97 1.16 1.60 1.79 1.44 1.63 1.96 2.16 1.43 1.61 2.01 2.18 2.57 2.76 typ 0.81 1.01 1.40 1.59 1.09 1.28 1.72 1.91 1.56 1.75 2.08 2.28 1.55 1.73 2.13 2.30 2.69 2.88 max 0.93 1.13 1.52 1.71 1.21 1.40 1.84 2.03 1.68 1.87 2.20 2.40 1.67 1.85 2.25 2.42 2.81 3.00 Unit V V V V V V V V V V V V V V V V V V
Pedestal level
Color burst low level
Color burst high level
Background color low level
Background color high level
Trimming level 0
Trimming level 1
Character level
Timing Characteristics at Ta = -30 to +70C, VDD1 = 5 0.5 V
Parameter Minimum input pulse width Symbol tW (SCLK) tW (CS) tSU (CS) tSU (SIN) th (CS) th (SIN) tword twt SCLK CS (the period while CS is high) CS SIN CS SIN The time to write 8 bits of data The RAM data write time Conditions min 200 1 200 200 2 200 4.2 1 typ max Unit ns s ns ns s ns s s
Data setup time
Data hold time
One word write time
Serial Data Input Timing
No. 4841-4/12
Serial to parallel converter
8-bit latch + command decoder Horizontal direction character size register Vertical direction character size register Display control register Horizontal display position register Vertical display position register Blinking and reversal control register RAM write address counter
System Block Diagram
Horizontal display position detection
Vertical display position detection
Decoder
Horizontal size counter Vertical dot counter
Vertical size counter Horizontal dot counter
Blinking and reversal control circuit
Display RAM
LC74723, 74723M
Character control counter
Line control counter
Decoder
Font ROM
Sync detector
Character output dot clock generator
Timing generator
Synchronization signal generator
Character output control Background control Video output control
Shift register
Sync separator
Composite synchronization signal separation control
No. 4841-5/12
LC74723, 74723M Display Control Commands Display control commands are input as serial data in 8-bit units. Commands consist of a first byte that includes the command identifier code and data in the following second byte. The LC74723 supports the following six commands. 1. 2. 3. 4. 5. 6. COMMAND0: Set display memory (VRAM) write address COMMAND1: Set up display character data write COMMAND2: Set vertical display start position and vertical character size COMMAND3: Set horizontal display start position and horizontal character size COMMAND4: Display control COMMAND5: Display control
Display Control Command Table
First byte Command Command identifier code 7 COMMAND0 (Set write address) COMMAND1 (Write character) COMMAND 2 (Vertical display start position and vertical character size) COMMAND3 (Horizontal display start position and horizontal character size) COMMAND4 (Display control) COMMAND5 (Synchronization signal control) 1 1 1 1 1 1 6 0 0 0 0 1 1 5 0 0 1 1 0 0 4 0 1 0 1 0 1 3 V3 0 0 EGP 2 V2 0 VS 20 HS 20 Data 1 V1 0 0 0 0 V0 0 VS 10 HS 10 SYS RST INT 7 0 at 0 0 0 -- 6 0 0 FS LC EGL -- 5 0 c5 VP 5 HP 5 NON -- 4 H4 c4 VP 4 HP 4 EG -- Second byte Data 3 H3 c3 VP 3 HP 3 BK 1 -- 2 H2 c2 VP 2 HP 2 BK 0 -- 1 H1 c1 VP 1 HP 1 RV -- 0 H0 c0 VP 0 HP 0 DSP ON --
TST RAM OSC MOD ERS STP 0 PH RSN
Once written, the command identifier code in the first byte is stored until the next first byte is written. However, when the display character data write command (COMMAND1) is written, the LC74723 locks into the display character data write mode, and another first byte cannot be written. When a high level is input to the CS pin, the LC74723 is set to COMMAND0 (display memory write address setting mode). 1. COMMAND0 (Display memory write address setting command) * First byte
DA 0 to 7 7 6 5 4 3 Register name -- -- -- -- V3 Contents State 1 0 0 0 0 1 0 1 0 1 0 1 Display memory address (0 to 9 hexadecimal) Command 0 identification code Set display memory write address. Function Remarks
2
V2
1
V1
0
V0
No. 4841-6/12
LC74723, 74723M * Second byte
DA 0 to 7 7 6 5 4 Register name -- -- -- H4 Contents State 0 0 0 0 1 0 1 0 1 0 1 0 1 Display memory address (0 to 17 hexadecimal) Function Second byte identification code Remarks
3
H3
2
H2
1
H1
0
H0
Note: The register states are all set to zero when the LC74723 is reset with the RST pin.
2. COMMAND1 (Display character data write setup command) * First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register name -- -- -- -- -- -- -- -- Contents State 1 0 0 1 0 0 0 0 Command 1 identification code Set up display character data write. When this command is input, the LC74723 locks into the display character data write mode until the CS pin goes high. Function Remarks
* Second byte
DA 0 to 7 7 6 5 Register name at -- c5 Contents State 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 Character code (00 to 3F hexadecimal) Character attribute off Character attribute on Function Remarks
4
c4
3
c3
2
c2
1
c1
0
c0
Note: The register states are all set to zero when the LC74723 is reset with the RST pin.
No. 4841-7/12
LC74723, 74723M 3. COMMAND2 (Vertical display start position and vertical character size setting command) * First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register name -- -- -- -- -- VS20 -- VS10 Contents State 1 0 1 0 0 0 1 0 0 1 1H per dot 2H per dot First line vertical character size 1H per dot 2H per dot Second line vertical character size Command 2 identification code Set vertical display start position and vertical character size. Function Remarks
* Second byte
DA 0 to 7 7 6 Register name -- FS VP5 (MSB) VP4 Contents State 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 The vertical display start position is set by the 6 bits VP0 to VP5. The weight of the low-order bit is 2H. Function Second byte identification code Crystal oscillator frequency: 2fsc Crystal oscillator frequency: 4fsc If VS is the vertical display start position then: VS = H x (2 2n VPn)
n=0 5
Remarks
5
4
H: the horizontal synchronization pulse period
3
VP3
2
VP2
1
VP1 VP0 (LSB)
0
Note: The register states are all set to zero when the LC74723 is reset with the RST pin.
4. COMMAND3 (Horizontal display start position and horizontal character size setting command) * First byte
DA 0 to 7 7 6 5 4 3 Register name -- -- -- -- EGP Contents State 1 0 1 1 0 1 0 1 0 0 1 1Tc per dot 2Tc per dot First line horizontal character size Correction: on Correction: off 1Tc per dot 2Tc per dot Trimming specifications when the horizontal character size is doubled Second line horizontal character size Command 3 identification code Set horizontal display start position and horizontal character size. Function Remarks
2 1 0
HS20 -- HS10
No. 4841-8/12
LC74723, 74723M * Second byte
DA 0 to 7 7 6 5 Register name -- LC HP5 (MSB) HP4 Contents State 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function Second byte identification code An LC oscillator is used for the dot clock A crystal oscillator is used for the dot clock If HS is the horizontal display start position then: HS = Tc x (2 2n HPn)
n=0 5
Remarks
Selects the dot clock used for horizontal direction character display.
4
Tc: The oscillator period of the OSCIN and OUT pin oscillator in operating mode The horizontal display start position is set by the 6 bits HP0 to HP5. The weight of the low-order bit is 2Tc.
3
HP3
2
HP2
1
HP1 HP0 (LSB)
0
Note: The register states are all set to zero when the LC74723 is reset with the RST pin.
5. COMMAND4 (Display control command) * First byte
DA 0 to 7 7 6 5 4 3 Register name -- -- -- -- TSTMOD Contents State 1 1 0 0 0 1 0 1 0 1 0 1 Reset all registers and turn the display off. Erase display RAM (set to 3F hexadecimal) Do not stop the crystal oscillator or LC oscillator circuits. Stop the crystal oscillator or LC oscillator circuits. Normal operating mode Test mode This bit must be zero. The RAM erase operation requires about 500 s (It is executed in the DSPOFF state.) Valid when character display is off in external synchronization mode. Reset occurs when the CS pin is low, and the reset is cleared when CS is high. Command 4 identification code Set display control. Function Remarks
2
RAMERS
1
OSCSTP
0
SYSRST
* Second byte
DA 0 to 7 7 6 Register name -- EGL Contents State 0 0 1 0 1 0 1 0 1 0 2 BK0 1 1 RV 0 1 0 1 Blinking on Reverse (character reversing) off Reverse (character reversing) on Character display off Character display on Function Second byte identification code Trimming level 0 (VBK0) Trimming level 1 (VBK1) Interlace (256.5 H per field) Non-interlace (263 H per field) Trimming off Trimming on Blinking period: about 0.5 s Blinking period: about 1.0 s Blinking off Blinking state switching When blinking is specified for reversed characters, the blinking will be between normal character and reversed character display. Trimming level switching Remarks
5
NON
Interlace/non-interlace switching
4
EG
3
BK1
0
DSPON
Note: The register states are all set to zero when the LC74723 is reset with the RST pin.
No. 4841-9/12
LC74723, 74723M 6. COMMAND5 (Display control command) * First byte
DA 0 to 7 7 6 5 4 3 2 Register name -- -- -- -- -- PH 1 0 1 RSN 1 0 INT 0 1 External synchronization signal detection control: Enabled External synchronization Internal synchronization Blue background External synchronization signal detection control: Disabled Contents State 1 1 0 1 0 0 Green background Background color switching (Only valid in NTSC mode, only a blue background color is supported in PAL-M mode.) External synchronization signal detection control Judges whether the signal has gone from present to absent or from absent to present. External/internal synchronization switching Command 5 identification code Synchronization signal control setup Function Note
Note: The register states are all set to zero when the LC74723 is reset with the RST pin.
Display Screen Structure The display consists of 24 characters x 10 rows for a maximum of 240 characters. The maximum number of characters is reduced when the character size is enlarged. Display memory addresses are specified as row (0 to 9 decimal) and column (0 to 23 decimal) addresses. Display Screen Structure (display memory addresses)
No. 4841-10/12
LC74723, 74723M Composite Video Signal Output Level (internally generated level) CVOUT output level waveform (VDD2 = 5.00 V)
Output level VCHA: Character VRSH: Background color high VCBH: Color burst high VRSL: Background color low VBK1: Trimming VBK0: Trimming VPD: Pedestal VCBL: Color burst low VSN: Sync Note: VDD2 = 5.00 V
Output voltage [V] 2.69 2.08 1.72 1.56 2.13 1.55 1.40 1.09 0.81
Output voltage [V] 2.88 2.28 1.91 1.75 2.30 1.73 1.59 1.28 1.01
No. 4841-11/12
LC74723, 74723M
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of June, 1997. Specifications and information herein are subject to change without notice. No. 4841-12/12

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